1. Field of the Invention
The present invention relates to a semiconductor memory device in which a memory transistor having a floating gate, serves as a memory cell.
2. Description of the Related Art
Among EEPROMS, the NAND-type EEPROM is known as being capable of a high degree of integration. In the NAND-type EEPROM, the memory transistor constituting one memory cell has a MOSFET structure as shown in FIG. 1, in which, a floating gate 93 and a control gate 94, completely surrounded by an insulation film so as to have no connection with the outside, are laminated onto a substrate 90 in which there are a source 91 and a drain 92. A plurality of such memory cells each having the above-described structure are arranged in a matrix. With regard to the column direction, a plurality of memory cells 95 are connected with each other in series such as to commonly use the sources and drains as shown in FIG. 2. The memory cell located at one end of the series is connected to a bit line BL via a selection gate 96, whereas the one at the other end is connected to a source line S via a selection gate 97. With regard to the row direction, the control gates of a plurality of memory cells are connected in series, thus forming a word line WL.
Next, the read, erase and write operations of data of the NAND-type EEPROM will be described. In the following description, the state in which electrons are present in the floating gate is set as "0", and the threshold voltage of such a state is set within a range of 0.5 to 3.5V. On the other hand, the state in which electrons are not present in the floating gate is set at "1", and the threshold voltage of such a state is set at -1V or less.
Read
A reference voltage of 0V is applied to the control gate of a selected memory cell, whereas a power voltage Vcc (for example, 3.3V) is applied to the control gate of a non-selected memory cell. With this operation, all of the non-selected memory cells are rendered conductive. Selected memory cells are rendered non-conductive when the memory data is "0", and conductive when the memory data is "1". Therefore, data "1" or "0" of a selected memory cell can be read out based on whether or not a current flows through the data line.
Erase
Erase can be defined as extracting electrons from the floating gates of all the memory cells, that is, setting all the memory cells to "1". The erase is carried out on the memory cells all at once. A voltage of 0V is applied to the control gates and the selection gates of all the memory cells. An erase voltage VE (about 20V) is applied to the substrate. With this operation, electrons are discharged to the substrate from the floating gates of all the memory cells due to the tunnel effect.
write
A write voltage VPP (about 20V) is applied to the control gate of a selected memory cell, whereas a middle voltage VM (about 10V) is applied to the control gate of a non-selected memory cell. A voltage of 0V is applied to the bit line of the selected memory cell, whereas a middle voltage VM (about 10V) is applied to the bit line of each of the other memory cells. Thus, a high voltage of 20V is applied between the control gate and the channel of a selected memory cell, and therefore electrons are injected from the channel to the floating gate due to the tunnel effect, thus setting up the state of "0". On the other hand, no tunnel effect occurs between the control gate and the channel of a non-selected memory cell, thus maintaining the state of "1".
The write voltage VPP, the middle voltage VM and the erase voltage VE are obtained by boosting the power voltage Vcc (3.3V) using a high-voltage generating circuit. A conventional high voltage generating circuit consists of a boost circuit 102 including a plurality of charge pump circuits 101 connected to each other in multiple stages, and a voltage limiting circuit 103 connected to the charge pump circuit located at one terminal in the boost circuit 102. A charge pump circuit 101 is constituted so as to control the charge/discharge of a capacitor 106 by two MOSFETs 104 and 105. A plurality of charge pump circuits are connected to each other in such a manner that MOSFETs 105 are connected in series in order to allow common usage of sources and drains thereof. To the capacitor 106 of each charge pump circuit 101, clock signals .phi.1 and .phi.2 of two phases are supplied from a ring oscillator as shown in FIG. 4.
The voltage limiting circuit 103 consists of the number n (two in FIG. 3) of Zener diodes 107 connected in series. Where the Zener breakdown voltage VZ per one Zener diode is 10V, the voltage limiting circuit 103 limits the write voltage VPP and erase voltage VE to 10V.times.n.
In a NAND cell-type EEPROM, the time required to write data can be made shorter as the write voltage VPP is higher. Conventionally, this voltage, however, cannot be increased too much and there is a certain upper limit for the voltage for the following reason.
If the write voltage VPP is made too high when writing data, some electrons inevitably flow into the floating gate of the non-selected memory cell connected to the word line, and it is likely that the threshold voltage exceeds 3.5V. As a result, even if a power voltage of 3.3V is applied to the control gate of the non-selected memory cell when writing data, it cannot create a conductive state. In short, the problem in which it is impossible to read data from the selected memory cell, will occur. Such a phenomenon is known as an overwrite.
The overwrite phenomenon occurs due to a variation in the external temperature. When the external temperature varies, the Zener breakdown voltage of the Zener diode 107 increases. Accordingly, the write voltage VPP increases. As a result, the threshold value, in a range of 0.5V to 3.5V for a write time of 10.mu. sec where the write voltage VPP is, for example, 20V, is raised to be 3.5V or higher for the same write time of 10.mu. sec when the write voltage VPP increases to 23V.
In order to solve the problem of the overwrite phenomenon, an intelligent write method has been developed. According to this method, a series of operations in which writing of data is carried out at a constant write voltage VPP for a short period of time, and in which the data thus written is read out to be verified, are repeated until appropriate data is written.
In the meantime, the thickness of, for example, the oxide film varies from one product lot to another, one wafer to another and from one chip to another, due to an inevitable processing error. In accordance with such a variation of thickness, the capacity coupling ratio between the oxide film and the interlayer insulation film varies, and therefore the optimal values of the write voltage VPP and the erase voltage VE and the like vary from one product lot to another, one wafer to another and from one chip to another. Therefore, it is conventionally very difficult to optimize the write voltage VPP, the erase voltage VE and the like.